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  3. MPEG-2 Video Encoder IP Core, MPEG-2 Video/Audio Encoder IP Core

MPEG-2 Video Encoder IP Core, MPEG-2 Video/Audio Encoder IP Core

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Product Description

MPEG-2 Video/Audio Encoder IP Core (for Xilinx FPGAs: Spartan-6, Artix-7, Kintex-7, Virtex-6/7, and Zynq-7).

Features:

  1. Super low latency of less than 0.25ms
  2. Small silicon footprint
  3. Low power consumption
  4. All-hardware architecture

Key Features and Benefits

  • Compliance Standard: MPEG-2/H.262 (ISO/IEC 13818)
  • Output Bit Rates: 1-100Mbps, supports both VBR and CBR
  • Video Resolutions: Up to 1080i/p
  • Frame Rate: Up to 60fps
  • Supports Chroma Formats: 4:2:2 or 4:2:0
  • Output Format: MPEG-2 Elementary, or Transport Stream
  • Video Input Format: RGB or YUV or YCrCb
  • Power Consumption: 0.8w (Core only)
  • Latency: 0.25ms
  • Architecture: All-Hardware (without embedded processor)
  • Multi-Channel: Supports multiple channels with one engine or multiple engines
  • Conformant Standard for Audio: ISO/IEC 11172-3 (MPEG-1) Level 3
  • Supported Audio Sample Rates: 32 kHz, 44.1 kHz and 48 kHz.
  • Supported Audio Bit Rates: 32/40/48/56/64/80/96/112/128/160/192/224/256/320kbps

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
ARTIX-7SL Family XC7A50SL -2 Vivado 2020.2 100000 50000 50 60 0 0 1

IP Quality Metrics

General Information

This Data was Current On Feb 08, 2024
Current IP Revision Number 4.10
Date Current Revision was Released Jun 01, 2020
Release Date of First Version Mar 20, 2013

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 100
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Bitstream
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Other
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Artix-7
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques simulations
Custom FPGA Optimization Techniques MPEG-2 Encoder IP Core
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA N
Hardware Validation Platform Used SOC FMC-MCM-1000
Industry Standard Compliance Testing Passed Y
Specific Compliance Test MPEG-2
Test Date Mar 20, 2013
Are Test Results Available? Y