CPU less SATA Host IP core (SATA HCTL IP)
- Part Number: SATA3H-CPUless-IP
- Vendor: Design Gateway Co., Ltd.
- Partner Tier: Elite Certified
Product Description
Design Gateway SATA3 Host CPUless IP Core is designed to be an all-in-one system that contains the application layer, transport layer, and link layer in one IP. This helps the connection with the PHY layer implemented by the transceiver without CPU and DDR usage. The SATA Physical layer is designed by HDL code for controlling transceiver following SATA protocol and is the interface module connected between SATA3HCTL IP and SATA device. This SATA3 IP core PHY is provided in the reference design in the release stuff for the IP customer. The SATA3 host IP core features dgIF typeS user interface that is very easy to access and comes with control and data interface. For more detail, please visit http://www.dgway.com/SATA-IP_X_E.html
Key Features and Benefits
- Simple user interface by dgIF types
- Support four commands such as IDENTIFY DEVICE, SECURITY ERASE UNIT, WRITE DMA (EXT), and READ DMA (EXT)
- SATA application layer, transaction layer and link layer by hardware logic
- No need for external memory and CPU
- Compliant with the Serial ATA specification revision 3.0
- 2 x 4Kbyte FIFO for internal buffer
- Support SATA-III Speed by using 150 MHz for SATA clock and higher frequency for user clock
- Free HDL code of SATA3 PHY and the reference design in release stuff
- Reference design by using AB09-FMCRAID adapter board from Design Gateway
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU9P | -2 | Vivado 2020.1 | Y | 636 | 1597 | 1 | 0 | 0 | 1 | 500 |
| Zynq-UP-MPSoC Family | XCZU9EG | -2 | Vivado 2020.1 | Y | 656 | 1592 | 1 | 0 | 0 | 1 | 500 |
| Zynq-7000 Family | XC7Z045 | -2 | Vivado 2020.1 | Y | 563 | 1500 | 1 | 0 | 0 | 1 | 333 |
| KINTEX-U Family | XCKU040 | -2 | Vivado 2020.1 | Y | 632 | 1488 | 1 | 0 | 0 | 1 | 370 |
IP Quality Metrics
General Information
| This Data was Current On | Sep 04, 2024 |
| Current IP Revision Number | 1.3 |
| Date Current Revision was Released | Jul 09, 2018 |
| Release Date of First Version | Oct 09, 2014 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 16 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Kintex UltraScale |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | No |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | KCU105, ZCU106, VCU118,KC705, AC701, VC707, ZC706 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |