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  3. 10GbE TCP Offload Engine IP core (TOE10G-IP)

10GbE TCP Offload Engine IP core (TOE10G-IP)

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Product Description

TCP Offloading Engine (TOE10G) IP core is the epochal solution implemented without CPU. Usually TCP processing is complicated and needs expensive high-end CPU. Because TOE10G-IP core automatically takes over all functions of TCP/IP protocol which needs high-speed operation by hardware logic only. This IP product includes reference design for AMD FPGAs. It helps you to reduce development time.

Design Gateway provide demo file for AMD FPGA boards. You can evaluate TOE10G-IP core on real board before purchasing. Please visit http://www.dgway.com/TOE-IP_X_E.html

Key Features and Benefits

  • All pure hardware 10GbE TCP/IP stack implementation
  • Support IPv4 protocol
  • Support Full Duplex
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • One clock domain interface by fixed 156.25 MHz clock frequency
  • Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
  • Rerference design is included in IP core product

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado 2020.1 Y 704 3807 34 0 0 0 156
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado 2020.1 Y 736 3806 34 0 0 0 156
VIRTEX-7X Family XC7VX485T -2 Vivado 2020.1 Y 1347 3828 36 0 0 0 156
KINTEX-7 Family XC7K325T -2 Vivado 2020.1 Y 1326 3827 36 0 0 0 156
Zynq-7000 Family XC7Z045 -2 Vivado 2017.4 Y 1361 3827 36 0 0 0 156
KINTEX-U Family XCKU040 -2 Vivado 2017.4 Y 760 3808 34 0 0 0 156

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1.17
Date Current Revision was Released Mar 16, 2022
Release Date of First Version Oct 01, 2014

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 10
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Virtex UltraScale+
Software Drivers Provided? N/A
Driver OS Support NA

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZCU102, VCU118, KCU105, VC707, KC705, ZC706,
Industry Standard Compliance Testing Passed N
Specific Compliance Test N/A
Test Date May 01, 2022
Are Test Results Available? N