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100M/1G UDP/IP Stack

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Product Description

UDP/IP Full Accelerator for 100M/1G UDP/IP connections. Including UDP, IP, MAC Layer. 8-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

Key Features and Benefits

  • Round trip time of RTTmin ≥ 2.25 µs
  • UDP R/W latency of TUR(W) ≥ 0.75 µs
  • TCP R/W latency of TTR(W) ≥ 1.4 µs
  • Full line rate of TPRmax = 9.5896 Gbps
  • Point-to-point or LAN capable
  • Network Interface Card functionality with Bypass (optional)
  • Parameterizable for 8-bit (1GigE) or 128-bit (10GigE, 40GigE) data width
  • Highly modular UDP/IP stack implementation in synthesizable HDL

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -1 Vivado ML 2023.1 8865 41534 80 8 0 0 156

IP Quality Metrics

General Information

This Data was Current On Dec 05, 2023
Current IP Revision Number 2.7.1
Date Current Revision was Released Oct 16, 2023
Release Date of First Version Mar 11, 2015

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Bitstream, Netlist
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? Y
Driver OS Support PetaLinux

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation, UltraFast Design Methodology, Other Optimization Techniques
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4, AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa; Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZCU102
Industry Standard Compliance Testing Passed N
Are Test Results Available? N