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Unified Extensible Flash Controller

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Product Description

The MXIC Flash Host Controller is used to access Flash, including NOR and NAND Flash for high throughput and low pin count applications. The controller operates in one of these modes: I/O Mode, Linear Addressing Mode (Mapping Mode) and DMA Mode. In I/O Mode, software interacts closely with the flash device protocol. The software writes the flash commands and data to the controller using TXD Register. Software reads the RXD register that contains the data received from the flash device. This process is called as Buffer Read Write data transfer. In Linear Addressing Mode, after accepting AXI Burst Read or Write Command, the controller emulates the software to send Read or Write instructions to the flash device. Besides Buffer Read Write data transfer, the controller also supports DMA data transfer. A DMA master engine is included in the controller. The Host Controllers supports SDMA only. With AXI Slave interface, the Host Controller can also be a DMA Slave, which behaves like Linear Addressing Mode besides the flash instructions should be issued by software.

Key Features and Benefits

  • Data Rate: SDR(S), DDR(D)
  • Flexible I/O: Single Flash in 1-bit, 4-bit, 8-bit interface and Dual Flash in 1-bit, 4-bit, 8-bit stacked interface
  • Programmable bus protocol: SPI, QSPI, OCTA and ONFI
  • 32-bit AXI interface (Master) for DMA transfer
  • 32-bit AXI interface (Slave) for Linear Addressing Mode transfer
  • 32-bit AXI Lite interface (Slave) for I/O Mode transfer

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z014S -1 Vivado 2016.4 Y 4013 5621 2 0 0 0 200
Zynq-7000 Family XC7Z030 -1 Vivado 2016.4 Y 4619 5496 4 0 0 0 200

IP Quality Metrics

General Information

This Data was Current On Sep 08, 2020
Current IP Revision Number 003
Date Current Revision was Released Jan 07, 2020
Release Date of First Version Jan 07, 2020

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Model Formats NA
Integration Testbench Provided Y
Integration Test Bench Format(s) OVM System Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support Bare Metal & Linux

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques source code
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4, AXI4-Lite
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Assertion
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Zynq-7000
Industry Standard Compliance Testing Passed N
Are Test Results Available? N