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  3. GZIP/ZLIB/Deflate Data Compression Core

GZIP/ZLIB/Deflate Data Compression Core

  • Part Number: Zipaccel-C
  • Vendor: CAST, Inc.
  • Partner Tier: Elite Certified
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Product Description

ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards. The core receives uncompressed input files and produces compressed files. No post processing of the compressed files is required, as the core encapsulates the com-pressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input. The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible even in low-cost FPGAs, and latency can be as small as 13 clock cycles. ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best trade off for a specific system is facilitated by the included software model, and by support from our team of data compression experts.

Key Features and Benefits

  • Flexible architecture allows fine-tuning Throughput, Compression Efficiency, and Latency to match application requirements.
  • Compression efficiency can be on par with Unix/Linux max compression option (gzip -9)
  • Latency from 13 clock cycles (Static Huffman)
  • FPGA resources requirements from 15k LUTs
  • Supports Deflate (RFC-1951), ZLIB (RFC-1950) & GZIP (RFC-1952).
  • More than 100Gbps with one core instance, scalable to meet any throughput requirement

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU11P -1 Vivado ML 2023.2 0 8198 19 0 0 0 300
KINTEX-U Family XCKU085 -1 Vivado ML 2022.1 Y 0 4021 2 0 0 0 350
Kintex-UP Family XCKU9P -1 Vivado ML 2022.1 Y 0 3980 2 0 0 0 450
VERSAL_PREMIUM Family XCVP1202 -2 Vivado ML 2022.1 900 4058 1 0 0 0 450
Artix-UP Family XCAU25P -1 Vivado ML 2022.1 0 4019 2 0 0 0 500
KINTEX-7 Family XC7K325T -1 Vivado 2018.2 Y 2679 7012 5 0 0 0 200

IP Quality Metrics

General Information

This Data was Current On Oct 30, 2024
Current IP Revision Number 3.2f
Date Current Revision was Released Aug 19, 2024
Release Date of First Version Mar 09, 2012

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 17
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Model Formats C
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF & SDF
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex UltraScale
Software Drivers Provided? Y
Driver OS Support Linux Fedora 20 or later

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis; Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? No
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM; Mentor Questa; Cadence NC-Sim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KCU105
Industry Standard Compliance Testing Passed N/A
Are Test Results Available? N