GigE Vision IP Core (GigEVCore2.2)
- Part Number: GigEVCore2.2
- Vendor: Sensor to Image GmbH
- Partner Tier: Select Certified
Product Description
GigE Vision is a standard communication protocol for vision applications based on the well-known Ethernet technology. It allows easy interfacing between GigE Vision devices and PCs running TCP/IP protocol family. Sensor to Image offers a set of IP cores and a development framework to build FPGA-based products using the GigE Vision interface. Due to the speed of GigE Vision, especially at speeds higher than 1 Gb/s, senders and receivers require a fast FPGA-based implementation of the embedded GigE core. GigE Vision reference designs supporting speeds up to 25G are available for AMD 7 Series, Ultrascale and Ultrascale+ devices.
Key Features and Benefits
- Control Channel handled by embbeded CPU
- Full functional reference designs for sending (camera) or receiving (host) applications available
- Packet Resend, PTP/IEEE1588 and ACTION command handling in hardware supported
- Implementation of the AIA GigE Vision Protocol
- Hardware Implementation of Stream Channel to reach maximum troughput
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU9EG | -2 | Vivado 2019.1 | Y | 3164 | 13796 | 31 | 1 | 0 | 2 | 200 |
| ARTIX-7 Family | XC7A200T | -2 | Vivado 2019.1 | Y | 7998 | 19386 | 36 | 4 | 4 | 0 | 150 |
| Zynq-7000 Family | XC7Z020 | -1 | Vivado 2019.1 | Y | 3684 | 8406 | 15 | 1 | 2 | 0 | 150 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 2.2 |
| Date Current Revision was Released | Mar 16, 2023 |
| Release Date of First Version | May 01, 2009 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 120 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Source Code, Netlist |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq-7000 |
| Software Drivers Provided? | Y |
| Driver OS Support | embedded CPU: Linux; PC: Windows, LINUX and OSX |
Implementation
| Code Optimized for Xilinx? | N |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | Y |
| Coverage Metrics Collected | Assertion, Code, Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | AC701, KC705, ZC706, ZCU102,KCU105, KCU116, MVDK |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | AIA GigE Validation Framework |
| Test Date | Apr 18, 2023 |
| Are Test Results Available? | Y |