USB 2.0 On-The-Go (USB2_OTG)
- Part Number: USB2_OTG
- Vendor: ASICS World Service, Ltd.
- Partner Tier: Select
Product Description
A ‘Dual-Role’ USB 2.0 On-The-Go IP Core that operates as both a USB 2.0 peripheral or as a USB 2.0 OTG host in a point-to-point communications with another USB device. The USB OTG IP Core is fully USB 2.0 and USB 2.0 On-The-Go Supplement compliant. A USB OTG IP Core is ideal for applications where the target device must act as a peripheral and as a host, depending the situation. It provides portable devices with a cost-effective way of conducting point-to-point communications using the USB bus. A good example is a PDA which has to be a peripheral that can sync with a host PC, but can also be a host when a peripheral, such as a keyboard or a camera, is connected to it.
Key Features and Benefits
- High Speed, Full Speed and Low Speed Support.
- No local memory required.
- OPB, AHD or WISHBONE Bus Interface.
- Up to 16 endpoints supported.
- USB IF Certified HS-OTG IP Core.
- UTMI L2+ OR ULPI interface available.
- SRP and HNP protocols support.
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-7X Family | XC7VX485T | -2 | Vivado 2018.1 | Y | 1142 | 2968 | 1 | 0 | 0 | 0 | 150 |
| KINTEX-7 Family | XC7K325T | -1 | Vivado 2018.1 | Y | 1450 | 3480 | 1 | 0 | 0 | 0 | 135 |
| Zynq-7000 Family | XC7Z045 | -2 | Vivado 2018.1 | Y | 1517 | 3508 | 1 | 0 | 0 | 0 | 145 |
| KINTEX-U Family | XCKU040 | -2 | Vivado ML 2022.1 | 0 | 3548 | 92 | 0 | 0 | 0 | 220 | |
| VIRTEX-U Family | XCVU095 | -2 | Vivado 2020.1 | 1400 | 11000 | 1 | 0 | 0 | 0 | 165 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 2.8 |
| Date Current Revision was Released | Sep 22, 2014 |
| Release Date of First Version | Sep 26, 2005 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 32 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Model Formats | Other |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Virtex UltraScale |
| Software Drivers Provided? | Y |
| Driver OS Support | Standalone |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | none |
| Synthesis Software Tools Supported/Version | Vivado Synthesis / 2020.1 |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | AXI4-Lite |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Cadence NC-Sim / 10.2 |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | VCU108 |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | OTG 2.0 Compliance |
| Test Date | Jun 15, 2006 |
| Are Test Results Available? | N |