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  3. 10G Ultra-Low Latency Ethernet MAC / PCS / PMA

10G Ultra-Low Latency Ethernet MAC / PCS / PMA

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Product Description

The 10G Ultra-Low Latency Ethernet MAC / PCS / PMA is the industry leading solution for latency critical Ethernet applications such as high-frequency trading and data center Ethernet switches. The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances. The IP core supports full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.

Key Features and Benefits

  • Easy to integrate with Orthogone ULL 10G TCP/IP and UDP/IP core
  • Highly optimized implementation resulting in ultra-low latency and very low gate count
  • Frame-Check Sequence (FCS) insertion and verification at line rate
  • Supports 16b (644MHz) or 32b (322MHz) AXI-4 Stream User facing logic interface
  • Supports 16 or 32 bit PMA (SERDES) Interface

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-U_Alveo Family VU_ALVEO -3 Vivado ML 2021.2 Y 0 1400 0 0 0 0 644

IP Quality Metrics

General Information

This Data was Current On Oct 24, 2023
Current IP Revision Number 2.0
Date Current Revision was Released Sep 19, 2022
Release Date of First Version Jul 06, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 10
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Model Formats N/A
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Virtex UltraScale+
Software Drivers Provided? N/A

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Code, Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor Questa; Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Alveo
Industry Standard Compliance Testing Passed N
Are Test Results Available? N