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  3. CPU-less NVMe Host side IP core for PCIe Gen3 (NVMe-IP)

CPU-less NVMe Host side IP core for PCIe Gen3 (NVMe-IP)

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Product Description

NVMe-IP core is a standalone NVMe Host Controller designed for seamless integration with integrated PCIe Gen3 block on AMD FPGA devices. Eliminate the need for a CPU or external memory to simplify the systems complexity and achieve high-performance NVMe SSD interfacing. It's ideal for applications demanding simplicity, speed, and resource efficiency. Easily construct multi-channel RAID systems with exceptional performance and minimal FPGA resource usage. Accelerate your NVMe Storage development process with included reference designs for AMD FPGA boards, reducing both time and cost.

Key Features and Benefits

  • Implement application layer to access NVMe PCIe SSD without CPU and external memory (DDR)
  • Simple user control I/F and FIFO interface for data port (dgIF typeS)
  • Direct NVMe Gen3 SSD access without the need for CPU or external memory
  • Include 256 KB data buffer by BlockRAM
  • Support 7 commands, i.e. IDENTIFY, WRITE, READ, Shutdown, SMART, Secure Erase and Flush
  • exFAT & FAT32 file system management without CPU usage (Option)
  • Customize support. PCIe Switch support, Customize data buffer with URAM/BRAM
  • Available reference design: 1CH, 1CH with DDR, 2CH RAID0, 4CH RAID0 demo with AB17-M2FMC or AB18-PCIeX16 adapter board available on various AMD FPGA boards
  • Integrated PCIe Gen3 block interface: 128-bit AXI4 interface, configured by 4-lane PCIe Gen3

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado 2019.1 Y 859 2954 66 0 0 0 400
Zynq-UP-MPSoC Family XCZU7EV -2 Vivado 2019.1 Y 934 2955 66 0 0 0 400
VIRTEX-7X Family XC7VX690T -2 Vivado 2019.1 Y 1591 3204 66 0 0 0 300
VIRTEX-7X Family XC7VX485T -2 Vivado 2019.1 Y 1638 3203 66 0 0 0 300
KINTEX-7 Family XC7K325T -2 Vivado 2019.1 Y 1574 3204 66 0 0 0 300
ARTIX-7 Family XC7A200T -2 Vivado 2019.1 Y 1500 3089 66 0 0 0 225
Zynq-7000 Family XC7Z045 -2 Vivado 2019.1 Y 1532 3201 66 0 0 0 300
KINTEX-U Family XCKU040 -2 Vivado 2019.1 Y 842 2951 66 0 0 0 400

IP Quality Metrics

General Information

This Data was Current On Sep 04, 2024
Current IP Revision Number 4.4
Date Current Revision was Released Sep 07, 2023
Release Date of First Version Jun 01, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 56
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? SDF
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N
Driver OS Support NA

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KCU105, VC707, ZCU102, ZCU106, VCU118, KCU116
Industry Standard Compliance Testing Passed N
Are Test Results Available? N