Product Description
The 25G MAC/PCS core provides high performance connectivity to significantly increase the efficiency and rate of data transfer in Virtex UltraScale FPGAs. Full RTT round trip time is 119.5ns, including all clock domain FIFOs and clock correction logic.
Key Features and Benefits
- Cut-through mode
- Designed to IEEE 802.3by specifications, 25GBASE-R
- Combined 7930 LUTs
- Deficit Idle Count / Programmable IFG– Minimize IFG
- Fault Management, BER monitoring
- Statistics counters for frames and bytes sent/received, size bins, FCS errors, broadcast
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-U Family | XCVU095 | -2 | Vivado ML 2022.1 | 0 | 7930 | 2 | 0 | 0 | 4 | 390 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 2.1 |
| Date Current Revision was Released | Jan 19, 2023 |
| Release Date of First Version | Sep 19, 2016 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 8 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist, Bitstream |
| High-Level Model Included? | N |
| Model Formats | Encrypted RTL |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq UltraScale+ MPSoC |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Stream |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | Y |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim; Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | N |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |