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  3. H.265/HEVC Encoder IP Core

H.265/HEVC Encoder IP Core

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Product Description

H.265/HEVC Encoder IP core

Key Features and Benefits

  • HD and 4k Version

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z035 -2 Vivado 2020.2 0 150000 10000 0 0 0 0

IP Quality Metrics

General Information

This Data was Current On Feb 08, 2024
Current IP Revision Number V1.1
Date Current Revision was Released Sep 10, 2016
Release Date of First Version Sep 10, 2015

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? N
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4, AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N