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  3. 40G/50G UDP/IP Hardware Protocol Stack

40G/50G UDP/IP Hardware Protocol Stack

  • Part Number: UDPIP-40G/50G
  • Vendor: CAST, Inc.
  • Partner Tier: Elite Certified
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Product Description

The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 50Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo Request and Reply Messages of the ICMP widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN. The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers mapped on an SoC bus.

Key Features and Benefits

  • 256-bit data-path and AXI-Stream data interfaces
  • Run time programmable network parameters: Local, Destination and Gateway IP address, Source and Destination UDP ports, MAC address
  • 1 to 32 UDP transmit and 1 to UDP 32 receive channels
  • Protocols, IPv4 without packet fragmentation, Jumbo and Super Jumbo Frames, ARP with Cache, ICMP (Ping), IGMP v3 (Multicast), UDP/IP Unicast and Multicast, DHCP, VLAN (802.1Q)
  • 10G, 40G, and 50G Ethernet

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU11EG -1 Vivado ML 2021.2 0 7127 17 0 0 0 312
VIRTEX-UP Family XCVU11P -1 Vivado 2017.4 0 8450 20 0 0 0 312
Kintex-UP Family XCKU9P -1 Vivado ML 2021.2 0 7124 17 0 0 0 312
VERSAL_AI_CORE Family XCVC1902 -2 Vivado ML 2021.2 0 7145 17 0 0 0 312
VIRTEX-7 Family XC7V585T -2 Vivado 2016.2 3114 7215 20 0 0 0 312
KINTEX-U Family XCKU060 -1 Vivado 2019.1 Y 0 7262 16 0 0 0 312

IP Quality Metrics

General Information

This Data was Current On Oct 07, 2024
Current IP Revision Number 3V05NS00
Date Current Revision was Released Sep 16, 2020
Release Date of First Version Jan 17, 2017

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 8
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF & SDF
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex UltraScale
Software Drivers Provided? N
Driver OS Support None

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis; Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code, Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Synopsys VCS; Mentor ModelSIM; Mentor Questa; Cadence NC-Sim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KCU105
Industry Standard Compliance Testing Passed N
Are Test Results Available? N