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  3. NVMe to NVMe Bridge

NVMe to NVMe Bridge

  • Part Number: IPC-NV171A-BR
  • Vendor: IntelliProp Inc.
  • Partner Tier: Elite Certified
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Product Description

The IntelliProp NVMe Bridge, IPC-NV171A-BR, utilizes the IntelliProp NVMe Host Core and the IntelliProp NVMe Device Core to create an NVMe protocol bridge. The bridge communicates with an NVMe host and an NVMe device. Throughout this document, these components of the system are referred to as the NVMe host and the NVMe device. The bridge also contains an NVMe host and NVMe device. These components are referred to as the Bridge NVMe host and the Bridge NVMe Device.

Key Features and Benefits

  • Data Command Handling – When the NVMe host requires a read or write command to an NVMe device, commands are written to host system memory dedicated to storing the command structure.
  • Data Command Completion Handling – When the NVMe device has completed a data command, a completion is posted back to the bridge.
  • Read Data Payload Transfer – The NVMe device will transfer frames of data to the bridge via the PCIe link when processing a read command
  • Write Data Payload Transfer – The NVMe device will initiate a data transfer from the bridge to the device via the PCIe link when processing a write command
  • Command and Data Ordering – The order of payload data transfers and command completions is established by the NVMe device
  • Physical Region Page list transfer – For commands that utilize a sector count large enough to require more than two data packets, the NVMe device will initiate a data transfer from the bridge to retrieve additional Physical Region Page descriptor entries.
  • Non data command handling – Non data commands include but are not limited to Flush Cache, Write Correctable, Compare and Dataset Management, as well as all administrative commands defined in the NVMe specification
  • Error Handling – Hardware asserts logic for processor to complete the error handling

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado ML 2022.2 Y 32661 153499 369 15 0 8 250
Zynq-UP-MPSoC Family XCZU19EG -2 Vivado ML 2022.2 Y 32843 154053 361 15 0 8 250
Kintex-UP Family XCKU11P -2 Vivado ML 2022.2 Y 33033 154950 356 15 0 8 250
VERSAL_AI_CORE Family XCVC1902 -2 Vivado ML 2022.2 Y 32290 151462 557 6 0 8 250

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1.84c
Date Current Revision was Released May 01, 2023
Release Date of First Version May 01, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 6
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? SDF
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N
Driver OS Support Yes

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Other
Static Timing Analysis Performed? Y
AXI Interfaces AXI4, AXI4-Lite
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Kintex Ultrascale
Industry Standard Compliance Testing Passed N
Are Test Results Available? N