2. Intellectual Property
  3. 1.7Gbytes/s FAID LDPC IP core for NAND flash controller

1.7Gbytes/s FAID LDPC IP core for NAND flash controller

  • Part Number: FAID.025.120105108.R01a
  • Vendor: Codelucida, Inc.
  • Partner Tier: Select
Request Information

Product Description

This LDPC IP core consists of an LDPC encoder and FAID™ decoder achieving a maximum decoding throughput of 1.7Gbytes/s for NAND flash controllers transitioning to support the next generation of NAND flash memories (such as 3D TLC, 3D QLC, and beyond). Both the encoder and decoder are based on proprietary and patented algorithms, and are included as separate synthesizable cores. The decoder performs hard-decision decoding and 2-bit soft-decision decoding (1 bit soft) in a single architecture. The FAID™ decoder provides increased error correction with a gain of 10%-15% in raw bit error rate (RBER) compared to min-sum-based decoders, while ensuring that a very low uncorrectable bit error-rate (UBER) of 1e-17 and lower is achieved with no error floor. Unlike standard LDPC decoders, the FAID™ decoder does not use a log-likelihood-ratio (LLR) table and provides robustness to the choice of soft reads leading to a simplified NAND media management for the flash controller.

The IP core has been validated in hardware and also with data collected from performing NAND characterization on 3D TLC and 3D QLC NAND chip samples.

Key Features and Benefits

  • Guaranteed to achieve very low frame error rate (FER) with no error floor.
  • ECC Performance (4KB, R=0.89):
    Hard-decision decoding: RBER=0.0067 @ FER =1e-6 (UBER =3e-11), RBER = 0.0058 @ FER=1e-11 (UBER=3e-16)
    2-bit soft-decision decoding (1 bit hard + 1 bit soft): RBER=0.0151 @ FER =1e-6, RBER = 0.0139 @ FER=1e-11
  • ECC Performance (4KB, R=0.86):
    Hard-decision decoding: RBER=0.0097 @ FER=1e-6, RBER=0.0087 @ FER=1e-11
    2-bit soft-decision decoding (1 bit hard + 1 bit soft): RBER=0.0202 @ FER=1e-6, RBER=0.0190 @ FER=1e-11
  • Max Throughput @500MHz (4KB, R=0.89):
    Decoder - 1.7Gbytes/s; Encoder - 1.24Gbytes/s
  • The total resource usage of the IP core (which includes the encoder and decoder) is provided in the product specs for a sample code configuration of 4KB, R=0.89.
  • Customizable for a different information length (1KB, 2KB, 4KB) + metadata and code rate (0.83 to 0.95).
  • Option to add feature to support multiple code rates in the same IP core to provide flexibility to change the code rate during processing.
  • Options to customize the interface and any other features of the core.

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU19EG -2 Vivado 2018.2 0 16983 47 0 0 0 500
Zynq-UP-MPSoC Family XCZU7EV -2 Vivado 2018.2 Y 0 16983 47 0 0 0 500
Kintex-UP Family XCKU15P -2 Vivado 2018.2 0 16983 47 0 0 0 500

IP Quality Metrics

General Information

This Data was Current On Mar 05, 2024
Current IP Revision Number R01a
Date Current Revision was Released Feb 11, 2020
Release Date of First Version Dec 31, 2018

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Model Formats Other
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N/A
Driver OS Support N/A

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Other Optimization Techniques
Custom FPGA Optimization Techniques Pipeline optimization, algorithmic modifications for efficient LUT usage
Synthesis Software Tools Supported/Version Other; Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Constrained random testing
Assertions Y
Coverage Metrics Collected Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim; Synopsys VCS; Mentor ModelSIM; Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZCU104 evaluation board, Ultra96-v2 development board, VC709 evaluation board
Industry Standard Compliance Testing Passed N
Are Test Results Available? N