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  3. SPMI-CTRL: MIPI SPMI Master or Slave Controller

SPMI-CTRL: MIPI SPMI Master or Slave Controller

  • Part Number: SPMI-CTRL
  • Vendor: CAST, Inc.
  • Partner Tier: Elite Certified
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Product Description

The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either master or slave nodes in an SPMI bus. The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check address and data parity. Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host. Integration of the core is extremely simple.

Key Features and Benefits

  • Small and Low Power: Less than 900 LUTs for either a master or a slave core, and direct serial clock usage to minimize switching activity when idle
  • Easy Integration: Directly bridges SPMI and AHB bus address space, and allows register access via 32-bit AMBA™ 2 APB bus
  • Run-time Debugging: Broadcasts SPMI bus state and device state, detects and reports errors, and can optionally captures all traffic in the SPMI bus
  • Low Host Overhead: Host is only required to initialize registers after a reset and define outgoing commands and arbitration levels
  • MIPI-SPMI v2.0 Master or Slave: Supports High Speed (HS) and Low Speed (LS) device classes, all commands and all arbitration levels.

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU5P -3 Vivado 2019.1 0 954 0 0 0 0 26
KINTEX-U Family XCKU025 -2 Vivado 2019.1 0 952 0 0 0 0 26
VERSAL_PRIME Family XCVM2902 -1 Vivado ML 2023.1 0 761 0 0 0 0 26
VIRTEX-UP Family XCVU19P -1 Vivado ML 2023.1 0 885 0 0 0 0 26
ARTIX-7 Family XC7A50T -1 Vivado 2019.1 0 1012 0 0 0 0 26

IP Quality Metrics

General Information

This Data was Current On Dec 08, 2023
Current IP Revision Number 1V14NS00
Date Current Revision was Released Oct 27, 2023
Release Date of First Version Nov 29, 2017

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 6
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF & SDF
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N
Driver OS Support N/A

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis; Mentor Precision; Synplicity Synplify; Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Code, Functional, Assertion
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ARTIX-7
Industry Standard Compliance Testing Passed N/A
Are Test Results Available? N