Product Description
The CoaXPress IP Core from KAYA Instruments provides a Multi-link high performance solution for rate demanding video applications. The IP core offers support for newest and industry leading Artix 7, Artix UltraScale+, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Zynq 7000, Zynq UltraScale+ and Versal FPGAs by AMD.
Key Features and Benefits
- CXP-12 support of up to 12.5Gbps high speed link and 41Mbps low speed link
- Embedded CRC-32 generate/check for streaming data packets
- Multiple CoaXPress links suited for applications demanding high throughput
- Build in FPGA SerDes , no need for additional design effort
- Multiple link rates support
- Multiple video stream support
- Compliant with JIIA CXP-001-2013 CoaXPress standard rev 1.0 / 1.1
- Compliant with JIIA CXP-001-2019 CoaXPress standard rev 2.0 / 2.1
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU9P | -2 | Vivado ML 2022.2 | Y | 0 | 18000 | 55 | 0 | 0 | 4 | 250 |
| Zynq-UP-MPSoC Family | XCZU9EG | -2 | Vivado ML 2022.2 | Y | 0 | 18000 | 55 | 0 | 0 | 4 | 250 |
| Kintex-UP Family | XCKU5P | -2 | Vivado ML 2022.2 | Y | 0 | 18000 | 55 | 0 | 0 | 4 | 250 |
| Zynq-UP-RFSoC Family | XCZU28DR | -2 | Vivado ML 2022.2 | Y | 0 | 18000 | 55 | 0 | 0 | 4 | 250 |
| VIRTEX-7X Family | XC7VX690T | -2 | Vivado 2019.1 | Y | 0 | 20000 | 56 | 0 | 0 | 4 | 250 |
| VIRTEX-7X Family | XC7VX485T | -2 | Vivado 2019.1 | Y | 0 | 20000 | 56 | 0 | 0 | 4 | 250 |
| KINTEX-7 Family | XC7K325T | -2 | Vivado 2019.1 | Y | 0 | 20000 | 56 | 0 | 0 | 4 | 230 |
| ARTIX-7 Family | XC7A200T | -2 | Vivado 2019.1 | Y | 0 | 20000 | 56 | 0 | 0 | 4 | 180 |
| Zynq-7000 Family | XC7Z045 | -2 | Vivado 2019.1 | Y | 0 | 20000 | 56 | 0 | 0 | 4 | 230 |
| KINTEX-U Family | XCKU040 | -2 | Vivado 2019.1 | Y | 0 | 18000 | 55 | 0 | 0 | 4 | 250 |
IP Quality Metrics
General Information
| This Data was Current On | Apr 15, 2024 |
| Current IP Revision Number | 7.0.4 |
| Date Current Revision was Released | Mar 07, 2023 |
| Release Date of First Version | Nov 15, 2015 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 50 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Bitstream, Netlist, Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis / 2017.4 |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite, AXI4-Stream |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators Supported | Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Evaluation boards |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |