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PTP Transparent Clock

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Product Description

The PTP Transparent Clock (TC) from NetTimeLogic is a fully scalable implementation of a Peer-To-Peer, One-Step Transparent Clock according to IEEE1588. It contains a Peer-Delay message processors which answers and measures the Peer-Delay to its neighbors and an On-The-Fly-Modifier unit which corrects the residence time of PTP Event-Messages. Each port is individual and only some common counter is shared between the ports. The number of ports can be freely chosen according to the requirements. All datasets and algorithms are implemented completely in HW. It supports the following: - P2P and E2E Delay Mechanism - Layer 2 and Layer 3 (IPv4, IPv6) Transport Mechanisms - Multicast, Unicast, Mixed - Default Profile, Power Profile, Utility Profile, 802.1AS, ITU-G8265-1, ITU-G8275-1, ITU-G8275-2

Key Features and Benefits

  • PTP Transparent Clock according to IEEE1588-2008
  • Intercepts path between MAC and PHY
  • Support for n-Ports
  • Support for Default Profile: Layer 2 (Ethernet) and Layer 3 (Ip) support
  • Support for Power Profile: C37.238-2011 including VLAN support
  • Support for Utility Profile: including HSR and PRP tag handling
  • One Step support
  • Peer to Peer (P2P) and End to End (E2E) delay measurement
  • Full line speed
  • AXI4 Light register set or static configuration
  • Datasets according to IEEE1588
  • MII/GMII/RGMII Interface support (optional AXI4 stream for interconnection to 3rd party cores)
  • Optional Management Message support
  • Timestamp resolution with 50 MHz system clock: 10ns

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
ARTIX-7 Family XC7A35T -1 Vivado ML 2022.1 Y 20000 20000 15 0 0 0 50

IP Quality Metrics

General Information

This Data was Current On Oct 07, 2024
Current IP Revision Number 2.3.2
Date Current Revision was Released Sep 27, 2024
Release Date of First Version Oct 01, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Model Formats None
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N
Driver OS Support N

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? No
Test Methodology Both
Assertions Y
Coverage Metrics Collected Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used NetTimeLogic AIONYX
Industry Standard Compliance Testing Passed Y
Specific Compliance Test ISPCS
Test Date Oct 07, 2024
Are Test Results Available? N