100G UDP/IP Stack
- Part Number: 100G UDP/IP Stack
- Vendor: Missing Link Electronics, Inc.
- Partner Tier: Premier
Product Description
UDP/IP Full Accelerator for 100G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.
Key Features and Benefits
- Point-to-point or LAN capable
- Network Interface Card functionality with Bypass (optional)
- Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU19EG | -2 | Vivado ML 2021.2 | 35460 | 166136 | 0 | 32 | 0 | 0 | 156 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 07, 2024 |
| Current IP Revision Number | 2023.2 |
| Date Current Revision was Released | Sep 23, 2024 |
| Release Date of First Version | Nov 15, 2018 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 0 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Bitstream, Netlist |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | N |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST; Synplicity Synplify; Mentor Precision; Other; Vivado Synthesis |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | AXI4, AXI4-Stream, AXI4-Lite |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | No |
| Test Methodology | None |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim; Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa; Synopsys VCS; Other |
Hardware Validation
| Validated on FPGA | N |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |