The AXI Debug Hub IP connects physical debug interfaces such as JTAG or HSDP to various debug cores (ILA, VIO, etc.) within a design. This allows runtime software such as Vivado to directly communicate with the debug IPs implemented in a design at runtime.
The AXI Debug Hub IP has dedicated AXI master and slave interfaces to connect to slave debug cores and NoC in Versal adaptive SoC devices.