Product Description
The AXI Debug Hub IP connects physical debug interfaces such as JTAG or HSDP to various debug cores (ILA, VIO, etc.) within a design. This allows runtime software such as Vivado to directly communicate with the debug IPs implemented in a design at runtime.
The AXI Debug Hub IP has dedicated AXI master and slave interfaces to connect to slave debug cores and NoC in Versal adaptive SoC devices.
Key Features and Benefits
- Support for connectition to up to 64 debug cores
- Configurable parameters for master interface connectivity
- Provides a communication path, using JTAG or HSDP debug interface, between Vivado Hardware Manager software and debug cores
- Support for up to 64 debug cores attached to the Debug Hub AXI ports
- Parameterizable AXI ports for connectivity to Network-on-Chip and other AXI master interfaces
- Optional BSCAN interface to provide a fallback path for debugging the designs, even in hung situation of AXI path
Support
Device Family:
Design Tools:
Featured Documents
Default
Default
Title
Document Type
Date