Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express

Versal™ devices contain two integrated blocks for PCI Express®: the integrated block for PCI in the interconnect for CCIX and PCI Express® (CPM) module, and the integrated block for PCIe in the programmable logic area (PL PCIE). This document covers the Versal™ adaptive SoC DMA and Bridge Subsystem for PCIe, which is used for data transfers between the Versal adaptive SoC integrated block for PL PCIE and the user logic. There are several functional modes for the subsystem. Select one of three options for data transport from host to user logic, or user logic to host. The functional modes are QDMA, AXI Bridge, and XDMA (PL PCIE4 only).