Versal Adaptive SoC CIPS Verification IP
- Bundled With:
- Vivado Design Suite
- License: End User License Agreement
Product Description
The Versal™ adaptive compute acceleration platforms Control, Interfaces, and Processing System (CIPS) Verification Intellectual Property (VIP) supports the functional simulation of Versal adaptive SoC applications. It is targeted to enable the functional verification of programmable logic (PL) by mimicking the processor system (PS)-PL interfaces and OCM memories of PS logic. This VIP is delivered as a package of System Verilog modules. VIP operation is controlled by using a sequence of System Verilog tasks.
Key Features and Benefits
- Narrow transfers are supported for 32/64-bit transfers.
- 8/16/32-bit width registers are supported.
- ACE interface supports only AXI4 traffic, all sideband signals are ignored.
- ACP interface supports limited AXI4 features.
- For ACP, AxSIZE is tied to 4 (128-bit).
- AxBURST = 1 (only INCR is supported).
- PL clock/PL reset/PS-PL/PL-PS interrupts supported in API.
Support
Featured Documents
Default
Default
Title
Document Type
Date