Product Description
The AMD LogiCORE™ AI Engine IP enables the configuration of the AI Engine Array Interface. This array is connected to the Network on Chip and to the programmable logic (PL) through tiles that are located in the AI Engine Array Interface. This IP allows the specification of the number of AXI4-Stream and memory mapped AXI interfaces with their respective width and direction and defines the clock driving the AI Engine array.
Key Features and Benefits
- Memory mapped AXI4 configuration interfaces.
- Memory mapped AXI4 master interfaces.
- AXI4-Stream master and slave interfaces with configurable data widths of 32, 64, or 128 bits.
- Option to enable registered interfaces to enable fast streams.
- Automatic association of programmable logic (PL) stream clocks.
Support
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