Product Specification

XQ Grade Virtex-4 FF668 100% Material Declaration Data Sheet

XQ Grade Virtex-4 FF1148 100% Material Declaration Data Sheet

Virtex-4 FPGA User Guide

XtremeDSP for Virtex-4 FPGAs User Guide

Xilinx Virtex-4 and Virtex-5 devices a have high-precision programmable delay element associated with every input pin. These delay elements, called IDELAY, can be used to implement an oversampler that uses very few FPGA logic resources and, more importantly, just a single DCM and two global clock resources to do 8X oversampling. This solution provides better jitter tolerance than techniques that use multiple DCMs.

The purpose of this notification is to announce qualification of new second source construction materials, and the addition of a second source supplier for Xilinx plastic flip-chip products. In addition, a mask set stepping introduction for select Virtex -4 FX products.

This notification is to inform you of the Xilinx test site transfer of all Aerospace Defense “XQ” I-grade and M-grade devices from Xilinx San Jose, California “XSJ” and/or Xilinx Dublin, Ireland “XIR” test sites to Xilinx Singapore “XAP” test site.

To announce conversion of substrate material changed from BT to ABF build-up for selected Aerospace Defense "XQ" Virtex -4 FPGA device/package.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To announce that Xilinx has qualified a new bumping supplier for Virtex -4QV FPGA space-grade devices in ceramic flip chip column grid array (CF) packages.

To inform Xilinx customers of the removal of Xilinx support for Parity Checking for PowerPC 405 in all Virtex -4 FX FPGAs for the "XC" Commercial "C", Industrial "I", and Aerospace/Defense "XQ" devices.

To inform customers that Xilinx is adding a new logistics service provider for our products.

To advise customers of a product marking change for Virtex -ll, Virtex -II Pro, and Virtex -4 FPGA Flip Chip packages

To inform customers that Xilinx is adding a final test site, Silicon Turnkey Solutions (STS), in the United States for all defense-grade XQ FPGA products. There is no change to the form, fit, or function of the devices with this change.

The purpose of this notification is to communicate substrate material change for Virtex®, Virtex®-II, Virtex®-II Pro, Virtex®-4 and Virtex®-5 FPGA packages.

The purpose of this notification is to communicate that Xilinx will continue supplying Eutectic bump from an additional bump factory at Siliconware Precision Industry Ltd. (SPIL) for the next few coming years for all Virtex -II Pro, Virtex -4, Virtex -5 and Virtex -6 FPGAs defense-grade “XQ” flip-chip products. As described in XCN16003, Xilinx has also qualified defense-grade 7 Series XQ FPGA product on the additional bump facility.

The purpose of this notification is to communicate that Xilinx defense-grade product chip-capacitor manufacturer will change the manufacturing location for chip-capacitors used in Xilinx defense-grade “XQ” products.

The purpose of this notification is to communicate that Xilinx is discontinuing SCD4095 part for multiple customers.

Announces that AMD-Xilinx is converting the bump to lead-free for Virtex-4/-5/-6 and Series 7 FPGAs Defense (XQ) and Space (XQR) flip-chip products.

The purpose of this notification is to communicate that Xilinx® is discontinuing selective Defense (XQ) and Space (XQR) FPGA products. This product discontinuance notice applies to all speed and temperature-grade variations.

Xilinx Defense-grade 7-Series FPGAs provide a broad portfolio of ruggedized, off-theshelf devices that reduce risk and deployment time with high levels of integration, high performance, high capacity, and built-in fail-safe Information Assurance (IA) and Anti-Tamper (AT) technology.