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        DesignCon 2019 – Xilinx 112G PAM4 and Samtec NovaRay Cable assemblies

        At DesignCon129, Xilinx and Samtec show the reality of 112G cabled backplanes. With 112G PAM4 signals generated, received and validated by the next generation Xilinx 112G PAM4 test device and the Samtec NovaRay cable assemblies carrying the data, this video shows realistic backplane lengths running at rates that are infeasible over traditional PCB interconnects.

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        DesignCon 2019 – Xilinx 112G PAM4 over Luxshare OSFP DAC copper cable

        At DesignCon 2019, Xilinx and Luxshare show 112G PAM4 operating over 1m of direct attach copper OSFP copper cabling. Watch to see how these companies are working together to enable the future of high speed connectivity.

        DesignCon 2019 – Xilinx 58 and 112G PAM4 SERDES operating over Molex high speed interconnect

        At DesignCon 2019, Xilinx and Molex show a pair of demonstrations. First, the Xilinx GTM 58G PAM4 SERDES found in Virtex UltraScale+ FPGAs operates over 3m of QSFP-DD Direct Attach Copper, facilitated by Molex Near-Stack high speed connectivity solutions. Next, the Xilinx 112G PAM4 test device operates over an evaluation Molex Impulse Orthogonal backplane, showing next generation interconnect today.

        112G Long Reach PAM4

        112G PAM4 is the next step on the industry's road to higher bandwidth. This demonstration illustrates the Xilinx vision for 112G for next generation systems.

        DesignCon 2019 – Xilinx 32G NRZ GTY and 58G PAM4 GTM operating over TE next generation connectivity

        At DesignCon 2019, Xilinx and TE work to show a pair of demonstrations. First, the 32G Xilinx GTY NRZ SERDES found in the UltraScale+ FPGAs is operating over the TE Sliver connectors. Next the Virtex UltraScale+ GTM PAM4 transceiver is sending data over a TE SFP-DD connector and Direct Attach Copper cable.

        100G Ethernet, 16nm UltraScale+ solution enhanced with an integrated RS-FEC module

        This video highlights the Xilinx integrated 100G Ethernet solution for 16nm UltraScale+ FPGAs and MPSoCs, enhanced with a Reed-Solomon Forward Error Correction module (RS-FEC) module based on IEEE the 802.3bj specification, enabling the use of low cost optics and direct attach copper interconnect.