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        DesignCon 2019 – Xilinx 32G NRZ GTY and 58G PAM4 GTM operating over TE next generation connectivity

        At DesignCon 2019, Xilinx and TE work to show a pair of demonstrations. First, the 32G Xilinx GTY NRZ SERDES found in the UltraScale+ FPGAs is operating over the TE Sliver connectors. Next the Virtex UltraScale+ GTM PAM4 transceiver is sending data over a TE SFP-DD connector and Direct Attach Copper cable.

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        DesignCon 2019 – Xilinx 58 and 112G PAM4 SERDES operating over Molex high speed interconnect

        At DesignCon 2019, Xilinx and Molex show a pair of demonstrations. First, the Xilinx GTM 58G PAM4 SERDES found in Virtex UltraScale+ FPGAs operates over 3m of QSFP-DD Direct Attach Copper, facilitated by Molex Near-Stack high speed connectivity solutions. Next, the Xilinx 112G PAM4 test device operates over an evaluation Molex Impulse Orthogonal backplane, showing next generation interconnect today.

        100G Ethernet, 16nm UltraScale+ solution enhanced with an integrated RS-FEC module

        This video highlights the Xilinx integrated 100G Ethernet solution for 16nm UltraScale+ FPGAs and MPSoCs, enhanced with a Reed-Solomon Forward Error Correction module (RS-FEC) module based on IEEE the 802.3bj specification, enabling the use of low cost optics and direct attach copper interconnect.

        56G PAM4 Transceiver Technology Demonstration

        In this video, we’ll show you the industry’s first programmable device running 56G transceivers. Based on the PAM4 signaling protocol, this forward looking technology will enable the next wave of Ethernet deployment by scaling 50G, 100G, and 400G port densities without increasing cost and power per bit.

        Xilinx 25G Interconnect: Kintex, Virtex and Zynq UltraScale+ Devices

        The breadth of interconnect running from 19 to 32Gb/s is quickly expanding. Learn how Xilinx UltraScale+™ FPGAs and MPSoCs enable the direct use of these interconnect, and how the KCU116 and VCU118 Evaluation Kits can jump start your transceiver based design.

        Xilinx Demonstrates Virtex UltraScale+ GTM Transceiver Driving 58G PAM4 over Legacy 100G Copper at XDF Silicon Valley 2018

        The Virtex® UltraScale+™ 58G PAM4 FPGA is capable of transmitting and receiving data over the most challenging of channels. In this live demonstration at XDF Silicon Valley, 58Gb/s was transmitted over 5m of QSFP28 Direct Attach Copper cabling and received by the GTM PAM4 transceiver. After this strenuous channel and being run at the maximum rate of the transceiver there were 0 post-FEC errors over multiple days of running live at XDF. For more information on how the Virtex UltraScale+ GTM transceiver can enable your PAM4 designs.