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        Accurate Logic & Signal Power Estimation In XPE

        Learn about one of the key accuracy improvements in XPE for UltraScale and UltraScale+ devices. Starting from XPE 2015.4, replaced 'fanout' logical representation with 'routing complexity' algorithm to address Logic & Signal power co-relation between XPE and Vivado Report Power.

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        XPE For Early Thermal Analysis

        Walk through an early thermal analysis using XPE at various phases of the design cycle including the device selection, design creation and thermal management phases. Positioning the importance of thermal analysis and recommended use model for system reliability with emphasis on the importance of thermal simulation during design creation and system debug cycles.

        Lowest Core Voltage Offering In UltraScale+

        Showcasing the lowest core voltage offering in UltraScale+ portfolio to achieve 2.4X performance per watt compared to 7-series devices. Vlow option enables customers to choose 50% lesser power at 1.2x higher performance, 2X larger device or 1.6x higher performance for same power budget.

        UltraScale architecture for the industry’s best utilization

        The UltraScale architecture, along with the Vivado Design Suite, introduce many innovations over traditional FPGA architectures that increase performance and reduce power consumption.

        Embedded Vision and I-IoT Highlights: Powered by Xilinx

        Watch how Xilinx customers are integrating programmable technologies into the latest Embedded Vision and Industrial IoT applications.

        Introduction to Xilinx 2D Barcode Markings

        This video provides an introduction to 2D marking changes occurring during 2016 and early 2017 for some Xilinx’s 28nm, 20nm and 16nm FPGAs and MPSoCs. This overview provides useful information including 2D marking trends, customer benefits, labelling and available online tools to interpret the new marking.