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        UltraScale+ Security Lock Before you Leave

        Learn how to enable bitstream encryption to secure your design. This video shows how to enable AES-256 GCM bitstream encryption to protect your design from unintended use or reverse engineering.

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        UltraScale+ SEU Solution Integration Test by Error Injection

        Learn how to use the SEM IP to inject errors into your design and see them corrected. This video shows how to send single and multi-bit error injection commands to the configuration RAM and explains how to exercise meaningful testing scenarios.

        FlexE for DCI Transport

        World’s first complete FlexE 1.0 solution showcasing bonding, sub-rating and channelization on UltraScale+ FPGAs. This solution demonstrates how multiple clients can be transported using FlexE and highlights the ability of FlexE to carry larger data pipes and match them to transport links for optimal utilization of the link budget. This solution allows network operators to maximize optical performance and lower operating costs over existing infrastructure.

        Industry’s First Gen3 x 16 PCIe Solution Built into a Programmable Device

        This video highlights the first ever Gen3 x16 PCI Express solution built in a programmable logic device and passed PCI SIG compliance testing in the 4/2016 workshop. The demo showcases PCIe up and running on a Virtex® UltraScale+™ FPGA-based board and connected to Intel’s Skylake processor.

        DMA for PCI Express

        This video walks through the process of creating a PCI Express solution that uses the new 2016.1 DMA for PCI Express IP Subsystem. The first part of the video reviews the basic functionality of a DMAs in PCI Express systems. Next, the new DMA for PCI Express Subsystem features are explained. Finally, an IPI design using this new DMA IP is created and the design is put in hardware the Linux software driver and application are used to exercise traffic over the PCIe link.

        Xilinx 25G Interconnect: Kintex, Virtex and Zynq UltraScale+ Devices

        The breadth of interconnect running from 19 to 32Gb/s is quickly expanding. Learn how Xilinx UltraScale+™ FPGAs and MPSoCs enable the direct use of these interconnect, and how the KCU116 and VCU118 Evaluation Kits can jump start your transceiver based design.