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        UltraScale+ SEU Solution Integration Test by Error Injection

        Learn how to use the SEM IP to inject errors into your design and see them corrected. This video shows how to send single and multi-bit error injection commands to the configuration RAM and explains how to exercise meaningful testing scenarios.

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        DMA for PCI Express

        This video walks through the process of creating a PCI Express solution that uses the new 2016.1 DMA for PCI Express IP Subsystem. The first part of the video reviews the basic functionality of a DMAs in PCI Express systems. Next, the new DMA for PCI Express Subsystem features are explained. Finally, an IPI design using this new DMA IP is created and the design is put in hardware the Linux software driver and application are used to exercise traffic over the PCIe link.

        Xilinx 25G Interconnect: Kintex, Virtex and Zynq UltraScale+ Devices

        The breadth of interconnect running from 19 to 32Gb/s is quickly expanding. Learn how Xilinx UltraScale+™ FPGAs and MPSoCs enable the direct use of these interconnect, and how the KCU116 and VCU118 Evaluation Kits can jump start your transceiver based design.

        UltraScale architecture for the industry’s best utilization

        The UltraScale architecture, along with the Vivado Design Suite, introduce many innovations over traditional FPGA architectures that increase performance and reduce power consumption.

        Xilinx Dynamic Function eXchange Training Series: Advanced Floorplanning

        This training video reviews floorplanning requirements and walks through the details of Expanded Routing, a Vivado technology that improves efficiency and routability for any Reconfigurable Partition in a DFX design.

        Xilinx Dynamic Function eXchange Training Series: Floorplanning

        This training video reviews the fundamental requirements for floorplanning Dynamic Function eXchange designs and provides techniques to improve efficiency and results for any DFX design.