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        Utilizing the Wide MUX Product Feedback in the DSP48E2 Slice

        How to use the new Wide MUX product feedback capability in the UltraScale architecture DSP48E2 slice. This video shows how tom implement a complex multiply accumulate function using a verilog CMACC template delivered with Vivado Design Suite 2016.1

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        UltraScale architecture for the industry’s best utilization

        The UltraScale architecture, along with the Vivado Design Suite, introduce many innovations over traditional FPGA architectures that increase performance and reduce power consumption.

        Utilizing the Squaring MUX in the DSP48E2 Slice

        Showing how to use the new capability of squaring the pre-adder output in the UltraScale architecture DSP48E2 slice. This video shows how to use the squaring MUX when implementing a squared difference accumulate function in Vivado HLS.

        Accelerating DSP Design Productivity with UltraScale and UltraScale+ FPGAs and MPSoCs

        Designers tasked with delivering more capability and performance in today's sophisticated DSP applications are increasingly turning to programmable logic for their hardware solutions. Xilinx UltraSCale and UltraScale+ series FPGAs meet this demand with a family of devices uniquely developed to address specific market needs including high performance, low cost, and low power. Xilinx UltraScale and UltraScale+ series DSP design platforms accelerate development of DSP applications by reducing schedule risk, enabling design reuse, and introducing new high-level design methodologies.

        DMA for PCI Express

        This video walks through the process of creating a PCI Express solution that uses the new 2016.1 DMA for PCI Express IP Subsystem. The first part of the video reviews the basic functionality of a DMAs in PCI Express systems. Next, the new DMA for PCI Express Subsystem features are explained. Finally, an IPI design using this new DMA IP is created and the design is put in hardware the Linux software driver and application are used to exercise traffic over the PCIe link.

        Xilinx 25G Interconnect: Kintex, Virtex and Zynq UltraScale+ Devices

        The breadth of interconnect running from 19 to 32Gb/s is quickly expanding. Learn how Xilinx UltraScale+™ FPGAs and MPSoCs enable the direct use of these interconnect, and how the KCU116 and VCU118 Evaluation Kits can jump start your transceiver based design.