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        Virtex UltraScale Compliancy to 25Gb Copper Interconnect for Data Center

        This video showcases the Xilinx Virtex UltraScale 30Gig GTY Transceiver’s compliancy to the most challenging and desired of Data Center Ethernet standards: the 100GBase-CR4 and 100GBase-KR4 electrical standards. As shown, Xilinx transceivers accomplish this through their superior high speed clocking performance and fully auto-adaptive equalization.

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        Interfacing to QSFP28, CFP2, CFP4 optics and more with UltraScale FPGAs

        System designers leverage FPGAs to talk to a wide variety of pluggable optics. Those can be anything from those old Gigabit Ethernet modules to the latest 400Gig Ethernet arrangements.

        XDF 2017 Keynote: Developing Cloud Scale FPGA Accelerations Using AWS F1

        Kicking off the first annual Xilinx Developer Forum in Silicon Valley, Gadi Hutt of Amazon presents the keynote address. Gadi discusses FPGA development and deployment of cloud-scale applications, showing you how to get started, building cloud scale applications, commercialization and development tool updates.

        Xilinx Developer Forum Frankfurt 2018 – Keynote Address by Amazon Web Services

        Gadi Hutt of Amazon Web Services delivers the opening keynote for the Xilinx Developer Forum in Frankfurt on January 9, 2018. Gadi explains the basics of Amazon EC2 F1 instances, how to accelerate Xilinx FPGAs in the AWS cloud, and most importantly how to accelerate your business.

        100G Ethernet, 16nm UltraScale+ solution enhanced with an integrated RS-FEC module

        This video highlights the Xilinx integrated 100G Ethernet solution for 16nm UltraScale+ FPGAs and MPSoCs, enhanced with a Reed-Solomon Forward Error Correction module (RS-FEC) module based on IEEE the 802.3bj specification, enabling the use of low cost optics and direct attach copper interconnect.

        UltraScale Integrated 100G Ethernet IP for 10x10G and 4x25G

        This video demonstrates how using an integrated Ethernet MAC can save power, integration time and logic utilization while delivering the highest possible flexibility.