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        Synthesizing the Design

        Get an overview of the synthesis process and where it fits in the overall RTL-to-bitstream flow. Covers setting up synthesis and managing source files, synthesis and project options, running synthesis, and checking results.

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        Advanced Synthesis using Vivado

        Learn how to identify timing bottlenecks in your design. Analyzing a design at the synthesis level is an effective way to rapidly improve its performance.

        Using Tcl Commands in the Vivado Design Suite Project Flow

        Overview of contents of a basic Vivado IDE Tcl script

        Running Design Rule Checks (DRCs) in Vivado

        Learn the definition of DRC, the recommended usage methodology and how to effectively use Design Rule Checks in Vivado to identify and resolve critical errors and warnings.

        Block Synthesis

        Compilation Units in Vivado Synthesis

        Learn about compilation units and how Vivado organizes them for mixed Verilog and SystemVerilog projects. Compilation units impact the scope of user definitions and also restrict the scope of compiler directives.