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        RF Data Converter Power Estimation

        Illustrates using the Xilinx Power Estimator tool to predict power consumption for the RF Data Converter IP for the Zynq® UltraScale+™ RFSoC.

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        Data Converter Driver Overview

        Demonstrates how to access the documentation for the Zynq® UltraScale+™ RFSoC, which includes APIs as well as example files, through the Vitis unified software platform.

        SD-FEC IP Configuration

        Step through configuring the Soft-Decision FEC IP for the Zynq® UltraScale+™ RFSoC using the Vivado IP integrator.

        Creating an ADC System in IPI

        Steps through configuring the ADC in the RF Data Converter IP for the Zynq™ UltraScale+™ RFSoC using the Vivado IP integrator.

        Creating a DAC System in IPI

        Steps through configuring the DAC in the RF Data Converter IP for the Zynq™ UltraScale+™ RFSoC using the Vivado IP integrator.

        Investigating Power Constraints

        Illustrates how to add power and environment constraints to a Versal™ ACAP design as well as utilize the power and timing analysis features available in the Vivado® Design Suite.