Isolation Design Flow

The ability to control system failure modes through fault-tolerant design requires an implementation methodology that ensures fault propagation can be controlled. AMD Isolation Design Flow (IDF) provides fault containment at the FPGA module level, enabling single-chip fault tolerance by various techniques including:

• Modular redundancy
• Watchdog alarms
• Segregation by safety level
• Isolation of test logic for safe removal

IDF, pioneered for government cryptographic systems, is also appropriate for avionics, functional safety-related electronics, industrial robotics, critical infrastructure, financial systems, and other high-assurance, high-availability, and high-reliability systems. The IDF is part of a spectrum of reliability technologies that when appropriately combined provide unmatched reliability, performance, and cost effectiveness.

In addition to its long heritage serving government grade cryptographic systems, the IDF is an integral part of the AMD IEC61508 (Industrial Functional Safety) certified tool chain.  Additionally, it can aid in meeting the requirements of the ISO26262 specification (Automotive Functional Safety).

* Only 7S50

The IDF is a methodology based on existing implementation tool flows (ISE design tools in this case).  Additional time spent floor-planning the design is done using existing constraint tools (PlanAhead / Vivado GUI). Verification of work products (pinout and routed design) are done with a separate and independent tool (either IVT or VIV for ISE or Vivado respectively).

Virtex 5 FPGAs

• SCC for Virtex 5
  XAPP1134, "Developing Secure Designs Using the Virtex 5 Family”, helps FPGA designers implement The AMD Isolation Design Flow for Fault-Tolerant Systems SCC technology.
  • Reference Design and Application Note for XAPP1134
    
    
• SCC Using ISE 11.4 / 11.5 Design Suite
  XAPP1135, "Single Chip Crypto Lab Using PR/ISO Flow with the Virtex 5 Family", helps FPGA designers implement The AMD Isolation Design Flow for Fault-Tolerant Systems SCC technology using ISE 11.4 / 11.5 Design Suite.
  • Reference Design And Application Note for XAPP1135
    
    
• SCC Using ISE 12.1 / 12.4  Design Suite
  XAPP1105, " Single Chip Crypto Lab Using PR/ISO Flow with the Virtex 5 Family for ISE Design Suite 12.1", helps FPGA designers implement The AMD Isolation Design Flow for Fault-Tolerant Systems SCC technology using ISE 12.1 / 12.4 Design Suite.
  • Reference Design And Application Note for XAPP1105
    

Spartan 6 FPGAs

• Isolation Design Flow (IDF) for Spartan 6
  XAPP1145, "Developing Secure Designs with the Spartan 6 Family Using the Isolation Design Flow", helps FPGA designers implement Safe and Secure designs.
  • Reference Design and Application Note for XAPP1145
    
    
• Isolation Design Flow Lab Using ISE 12.4 Design Suite
  XAPP1104, "Implementation of a Fail-Safe Design in the Spartan 6 Family Using ISE Design Suite 12.4", helps FPGA designers use the Isolation Design Flow by implementing a Secure Design.
  • Reference Design And Application Note for XAPP1104
    

7 Series FPGAs

ISE Design Suite

• Isolation Design Flow (IDF) Rules/Guidelines for 7 Series
  XAPP1086, "Developing Secure and Reliable Single FPGA Designs with The AMD Isolation Design Flow for Fault-Tolerant Systems 7 Series FPGAs Using the Isolation Design Flow", helps FPGA designers implement Safe and Secure designs.
  • Reference Design and Application Note for XAPP1086
    
    
• Kintex 7: Isolation Design Flow (IDF) Lab Using ISE 14.4 Design Suite
  XAPP1085, "7 Series Isolation Design Flow Lab Using ISE Design Suite 14.4", helps FPGA designers use the Isolation Design Flow by implementing a Secure Design.
  • Reference Design And Application Note for XAPP1085

Vivado Design Suite

• Isolation Design Flow (IDF) Rules/Guidelines for 7 Series (Vivado Tools)
  XAPP1222, "Isolation Design Flow for The AMD Isolation Design Flow for Fault-Tolerant Systems 7 Series FPGAs or Zynq 7000 SoCs (Vivado Tools)", helps FPGA designers implement Safe and Secure designs.
  • Reference Design and Application Note for XAPP1222
    
    
• Zynq 7000: Vivado Isolation Design Flow (IDF) Lab
  XAPP1256, "Zynq 7000 SoC Isolation Design Flow Lab (Vivado Design Suite 2015.2)", helps FPGA designers use the Isolation Design Flow by implementing a Secure Design.
  • Reference Design and Application Note for XAPP1256

Vivado Design Suite

• Isolation Design Flow (IDF) Rules/Guidelines for UltraScale+
  XAPP1335  "Isolation Design Flow for Zynq UltraScale+" describes how to implement security or safety critical designs using The AMD Isolation Design Flow for Fault-Tolerant Systems IDF with The AMD Isolation Design Flow for Fault-Tolerant Systems Vivado Design Suite.
  • XAPP1335: Isolation Design Flow for Zynq UltraScale+
  
  
• Vivado Isolation Verifier User GuideVivado Isolation Verifier User Guide
  Starting Vivado 2018.3, Vivado Isolation Verifier (VIV) is integrated with Vivado releases and supports UltraScale+ devices (including Zynq UltraScale+. This document describes the usage of new Vivado Isolation Verifier (VIV) to verify Isolation in a FPGA/PL design.
  • UG1291: "Vivado Isolation Verifier User Guide"
  
  
• Isolation Design Example for Zynq UltraScale+
  XAPP1336 Isolation Design Example for Zynq UltraScale+
  Describes the creation and implementation of a single chip general purpose 2 channel system using the Lower Power Domain (LPD) as one channel and a Triple Modular Redundant MicroBlaze in the PL.
  • XAPP1336: Isolation Design Example for Zynq UltraScale+
  • Reference Design for XAPP1336
  
  

IDF Verification tools (IVT and VIV) verify that an FPGA design partitioned into isolated regions meet the stringent standards for fail-safe design. IVT and VIV are used at two stages in the FPGA design cycle. They are used first, early in the flow, to perform a series of design rule checks on floorplans and pin assignments. After the design is complete, they are used again to validate that the required isolation is built into the design.

Isolation Verification Tool (IVT) for ISE Design Suite

IVT is an executable that runs outside of ISE but fully within the ISE environment. IVT runs as a set of Design Rule Checks (DRCs) required to prove the design being operated on is isolated. It outputs a graphical display of the design and a verbose text report.

• The IVT.zip file contains:
• IVT Executable
• Release Notes and Installation Guide
• License Agreement
• Lab

Note that the current version of IVT supports Virtex 5, Spartan 6, and the 7 series family of FPGAs and SoCs.

• Download the IVT package (ZIP)

Vivado Isolation Verifier (VIV) for Vivado Design Suite

VIV is Tcl based script that integrates with Vivado DRC engine. It is essentially a series of DRCs that are loaded into Vivado that perform all the checks required to prove a design is isolated. Unlike IVT, its ISE predecessor, VIV integrates into the development tool leveraging the user friendliness of the Vivado GUI but still maintaining an independent development path. Its output is integrated into the Vivado DRC GUI display as well as a text output as enabled by the Vivado DRC engine.

• The VIV.zip file contains:
• VIV Script
• Release Notes and Installation Guide
• License Agreement
• Lab (coming soon)

Note that the current version of VIV supports the 7 series family of FPGAs and SoCs in Vivadio 2015.1 and beyond.

• Download the VIV package (ZIP)

NOTE: Starting 2018.2 Vivado Isolation Verifier is integrated with Vivado Design Suite release and this support UltraScale+ devices (including Zynq UltraScale+). For more information refer to UG1291: Vivado Isolation Verifier User Guide.