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  3. Hardware Security Module (HSM)

Hardware Security Module (HSM)

  • Part Number: SCZ_iSE_XZU+_BA471
  • Vendor: Secure-IC SAS
  • Partner Tier: Select Certified
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Product Description

The HSM IP module is a Hardware Security Module for a wide range of applications. It is developed, validated and licensed by Secure-IC as an FPGA-based IP solution dedicated to the AMD Zynq UltraScale+ MPSoC platform. As the connectivity of industrial systems is growing, so is the need for data integrity and system authentication. A very important aspect of this embedded security is a hardware security module (HSM), a security enclave that provides secure key management and cryptographic processing.

This HSM IP module removes the need for a dedicated HSM device and it incorporates 2 solutions:

- The HSM hardware IP, to be implemented in programmable logic and ready to interface with with the Zynq UltraScale+ processing system.
- A software stack containing the HSM firmware, HSM driver code and an interface layer allowing integration.

Ideal for the following applications:
  • Industrial
  • Defence
  • Automotive
  • Smart metering
  • IoT
  • eHealth
  • Banking & finance
Configurable, scalable and flexible solution - the hardware security module can be scaled and configured to match any requirement, even for the most demanding applications. The size and performance of the solution can be adapted for a perfect application fit while leaving room in the FPGA for other critical applications.

Key Features and Benefits

  • Supports ISO26262
  • Flexible and scalable platform
  • Cryptographic operations offload: PK engine, Symmetric engine, Random number generator
  • Easy to integrate (AXI interface)
  • Flexible anti-tampering
  • Secure counter
  • Secure key storage
  • Secure key provisioning

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado 2018.3 Y 4148 19857 50 7 0 0 250

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1.14.16
Date Current Revision was Released Mar 02, 2020
Release Date of First Version Jan 25, 2015

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 3
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? Y
Driver OS Support Linux

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST; Synplicity Synplify; Vivado Synthesis
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim; Mentor ModelSIM; Synopsys VCS

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used zcu102
Industry Standard Compliance Testing Passed N
Are Test Results Available? N