TLS Handshake Hardware Accelerator
- Part Number: SCZ_SP_BA452
- Vendor: Secure-IC SAS
- Partner Tier: Select Certified
Product Description
The TLS handshake hardware accelerator is a secure connection engine that can be used to offload the compute intensive Public Key operations (Diffie-Helmann, Signature Generation and Verification).
It combines a load dispatcher and a configurable amount of instances of the Public Key Crypto Engine (SCZ_IP_BA414EP) benefiting from all features supported (i.e. RSA/DH/DHE and ECDSA/ECDH/ECDHE/X.25519/X.448 and more). The efficient dispatching to several dozens of SCZ_IP_BA414EP instances helps reaching maximum system performance.
This IP is made of a core and optional modules to connect the core to standard interfaces (PCIe, AXI_DMA…). In addition our drivers have an asynchronous API (or non-blocking API) which are integrated in OpenSSL Async.
Ideal for the following applications:- Cloud computing
- Data center
- HSM
- Firewall
- IKE-TLS/SSL connection engine
- Blockchain transactions
Key Features and Benefits
- RSA, ECC and more (RSA/DH/DHE, ECDSA/ECDH/ECDHE, X.25519/X.448, mbedTLS integration, SM2)
- > 1 GHz in 16nm
- 400-500 MHz on mid-range/high-end FPGA
- Very high performance on off-the-shelf FPGA
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU9P | -2 | Vivado 2018.3 | Y | 0 | 485228 | 492 | 2256 | 0 | 0 | 250 |
| KINTEX-U Family | XCKU115 | -2 | Vivado 2017.4 | Y | 0 | 48252 | 54 | 384 | 0 | 0 | 400 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 2.7 |
| Date Current Revision was Released | Aug 26, 2019 |
| Release Date of First Version | Mar 12, 2018 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 5 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Source Code, Netlist |
| Source Code Format(s) | VHDL, |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis; Synplicity Synplify |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Synopsys VCS; Cadence NC-Sim; Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Zynq 7 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |