Current Time 0:00
Duration 0:00
Loaded: 0%
Stream Type LIVE
Remaining Time 0:00
 
1x
    • Chapters
    • descriptions off, selected
    • captions off, selected

        100G Ethernet, 16nm UltraScale+ solution enhanced with an integrated RS-FEC module

        This video highlights the Xilinx integrated 100G Ethernet solution for 16nm UltraScale+ FPGAs and MPSoCs, enhanced with a Reed-Solomon Forward Error Correction module (RS-FEC) module based on IEEE the 802.3bj specification, enabling the use of low cost optics and direct attach copper interconnect.

        Related Videos

        56G PAM4 Transceiver Technology Demonstration

        In this video, we’ll show you the industry’s first programmable device running 56G transceivers. Based on the PAM4 signaling protocol, this forward looking technology will enable the next wave of Ethernet deployment by scaling 50G, 100G, and 400G port densities without increasing cost and power per bit.

        OFC 2020 Versal Premium Showcase: Versal Adaptive SoCs for Creators of the Highest Bandwidth, Most Secure Networks

        For those developing next generation highest speed, secure networks targeting emerging technologies and protocols, join Mike Thompson, Sr. Product Line Manager for an overview of integrated technologies in Versal adaptive SoC devices including 112G PAM4 transceivers, off-the-shelf Ethernet and OTN connectivity, encryption, PCIe Gen5, and large FPGA fabric that together minimize power consumption and time to market.

        DesignCon 2019 – Xilinx 58 and 112G PAM4 SERDES operating over Molex high speed interconnect

        At DesignCon 2019, Xilinx and Molex show a pair of demonstrations. First, the Xilinx GTM 58G PAM4 SERDES found in Virtex UltraScale+ FPGAs operates over 3m of QSFP-DD Direct Attach Copper, facilitated by Molex Near-Stack high speed connectivity solutions. Next, the Xilinx 112G PAM4 test device operates over an evaluation Molex Impulse Orthogonal backplane, showing next generation interconnect today.

        16nm UltraScale+ FPGA with Integrated RS-FEC

        Another industry first, this demonstration showcases the Xilinx 16nm Virtex UltraScale+ FPGA with integrated 100G Ethernet MAC and RS-FEC working in tandem to send data over challenging electrical or optical interconnects. Integration saves logic area, simplifies implementation and reduces power consumption on the increasingly popular 100G Ethernet interfaces or high speed backplane applications. RS-FEC enables the use of less expensive multi-mode fiber or copper interconnects and optical modules by correcting errors inherent to those systems.

        FlexE for DCI Transport

        World’s first complete FlexE 1.0 solution showcasing bonding, sub-rating and channelization on UltraScale+ FPGAs. This solution demonstrates how multiple clients can be transported using FlexE and highlights the ability of FlexE to carry larger data pipes and match them to transport links for optimal utilization of the link budget. This solution allows network operators to maximize optical performance and lower operating costs over existing infrastructure.